The PIC100 is ST’s first silicon photonics technology and one of the most efficient PICs on a 300 mm wafer, thus enabling 200Gbps/lane and even greater bandwidth in the future. Indeed, this is a highly symbolic launch as it inaugurates a long series of PICs that will bring new efficiencies to data centers, AI clusters, and other optical networking appliances. ST knows the market well since many pluggable optical transceivers are already using our BiCMOS B55. By launching a more efficient PIC and a next-generation B55X using silicon germanium and a 55 nm process node, makers of pluggable transceivers can provide new efficiency ratings and performance, which are essential for the democratization of faster communication standards.
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PIC100: Finding the balance between performance and efficiency
The problem of heat dissipation
Anyone who has ever dealt with fiber communication knows that pluggable optical transceivers can get very hot, very quickly. In fact, while pluggable modules saw their power consumption steadily decrease since 2010, we are currently seeing an increase since 2022, according to Effect Photonics. As the bandwidth leaps massively, it becomes much harder to keep temperatures in check. The problem is that while servers need greater data throughput for AI and other data-intensive applications, high heat can cause serious challenges, such as performance degradation and reliability issues. Moreover, data centers strive to be more sustainable and efficient, but hotter and more demanding optical transceivers run counter to these objectives.
PIC100’s solutions to lower losses
To improve efficiency, the PIC100 features a best-in-class silicon waveguide loss down to 0.4dB/cm and a silicon nitride waveguide loss as low as 0.5 dB/cm. Moreover, the PIC100 still offers a Mach-Zehnder Modulator (MZM) with a bandwidth of 50 GHz and a high-speed photodetector up to 80 GHz. Put simply, the PIC100 is unique because of the integration of all these state-of-the-art devices in the same 300 mm stack.
Efficiency is also the reason why we adopted an edge coupler. Many in the industry tend to adopt grate couplers because it can help them save costs during testing and the initial alignment process. For instance, grating couplers allow wafer-level tests and offer a more flexible placement. However, they suffer from greater losses due to greater scattering and a more significant mismatch between the coupler and the fiber. By adopting an edge coupler, we can better match the fiber mode to the on-chip SiN waveguide, which results in a far more efficient coupling with losses below 1.5 dB.
ST’s 300 mm fab
Additionally, while the PIC100 provides some of the best performance and efficiency ratings in this category, it is also manufactured on larger wafers in our 300 mm fab in Crolles, France, making the technology vastly more cost-effective and, therefore, accessible to more customers. Since ST is Integrated Device Manufacturer, we have the production lines, supply chain mastery, and lithographic expertise to produce a modern PIC at scale. It’s another reason why we are launching the PIC100 today. As data centers increasingly rely on integrated photonics, we are uniquely positioned to offer power-efficient devices, large volumes, and cost-effective solutions.
ST’s PIC: looking at the future of silicon photonics in data centers
An easier upgrade path toward 1.6Tb/s transceivers
ST customers are already working on 800Gb/s and 1.6Tb/s pluggable modules, making today’s PIC100 launch meaningful while ramping up from the second half of 2025. This announcement thus marks the beginning of a new era, as makers are already taking advantage of ST’s PIC to 200Gbps/lane pluggable transceivers. As these QSFP56 modules have suffered from shortages, our new device should help alleviate these issues and provide an intermediate step between 100G and 400G interfaces, thus enabling data centers to upgrade their infrastructure gradually. It also explains why AWS is already working with ST and the leading optical module provider to use the PIC100 in their data centers.
A roadmap towards 400Gbps/lane and GPU-x optical links
While we are not providing any release dates at this point, we are committed to creating PICs supporting 400Gbps/lane that will scale alongside modern data centers. As AI trains on an ever-increasing corpus of information, and GPUs’ massive parallelism demands a constant and tremendous flow of data, ensuring the creation of faster and more efficient transceivers becomes essential. Hence, pluggable module makers have the assurance that they can continue to source their PIC from ST for many generations to come.
Additionally, to further improve efficiency, ST is announcing the upcoming release of the BiCMOS B55X. The successor of the B55 will further improve efficiency thanks to its use of silicon germanium and a 55 nm process node. Compared to a system that only uses a PIC100 with a competing BiCMOS, using both the PIC100 and the B55X should increase efficiency by about 15%. ST is also working on a through-silicon-via-brick (TSV) and compact modulators to enable the use of our PIC in GPU-to-X optical interconnection, thus allowing high-speed communication in chiplet configurations.
