Power consumption in modern data centers is skyrocketing, driven by increased usage of digital ASICs whose continuous power requirements can reach hundreds of Watts. At the recent ST Developers Conference, ST’s Paolo Sandri discussed the challenges faced by administrators of today’s data centers and the power distribution architecture options offered by ST to address the demands of low voltage, high current applications.
Data centers are evolving. They are no longer required to efficiently power basic CPUs operating at 100 Watts. Instead, they must provide high power densities to a growing range of processors that require higher current levels to operate efficiently. These include graphics processing units (GPUs), tensor processing units (TPUs) and networking ASICs. Using a traditional 12V power distribution bus to meet these increasing power requirements is no longer effective, and new power distribution architectures are available to meet these needs.
An effective way to improve power delivery is to move from the traditional 12V distribution bus to a 48V DC bus. However, 48V DC bus power distribution poses a few challenges in terms of conversion efficiency, power density, and total BOM optimization. ST offers a wide set of architectures to fit a range of needs when converting from 48V to either an intermediate bus or directly to Power over Load (POL) to applications that require high power densities.
Two-step power conversion architectures
The architectures proposed for the intermediate bus conversion can either provide a two-step regulated output (for example 12V) or a two-step unregulated bus linked to the input voltage by a defined conversion ratio (for example if the conversion ratio is 4:1 the Vout will be Vin/4). For both these architectures, challenges on efficiency and power density are addressed with ST solutions that can deliver power from a few hundred Watts to multiple Kilowatts.
For unregulated conversion, ST proposes a switched tank converter (STC) intermediate bus architecture. This is a relatively simple architecture designed to deliver 12V output from an input voltage ranging from 40V to 60V, a traditional 4 to 1 conversion ratio. One of the benefits of this architecture is its high power density and 98 percent peak efficiency at 360W. It is also built with off-the-shelf components so it offers low BOM costs. An unregulated architecture is sufficient for straightforward data center applications such as operating CPUs and DDRs, but if your platform includes certain sensitive applications, or PCI Express connectors or hard disk drives, you will need regulated conversion.
For regulated conversion, ST suggests a stacked buck (STB) intermediate bus architecture. The sweet spot for this architecture is input voltage ranges from 36 to 60 volts with 12 Volt outputs, with 800 watts thermal design power. As above, the primary benefit of this architecture is its high efficiency (at 54 volts, it achieves over 96 percent efficiency with power output of 721 Watts) and similarly low off-the-shelf component costs. In addition, this stacked buck architecture is scalable, with the potential of joining up to four cells for 3.2 kilowatts of power. Because it offers regulated current, this architecture is recommended for data center environments that include sensitive arrays such as tensor processing units or PCI Express equipment.
Direct single-step conversion architectures
Another conversion option from the 48V DC bus is the direct conversion to POL, where the architecture is designed to deliver power directly to the digital ASIC whose core typically requires several hundred watts. Direct conversion power delivery, besides requiring high efficiency and power density optimization, also demands to address a few other key challenges, such as the need to sink current in order to comply with intake requirements.
Direct conversion from 48V to POL is an interesting architecture because it opens the door to implementers of very high-density modules. This architecture converts from 40V to 60V input range directly down to a 1.8V GPU or TPU or other high power density applications in a single conversion, achieving a power density of 100 Watts per square inch and greater than 93 percent peak and flat efficiency. The design combines a quasi-resonant controller and a transformer and will require a more tailored approach in components procurement than the two-step conversion architectures above, which use off-the-shelf components.
To address the complexities of designing these direct conversion architectures, ST has joined other electronics manufacturers in the Power Stamp Alliance to define a standard product footprint and pin-out design for 48V direct conversion DC-DC modules, aka “power stamps.” Creating the alliance and publishing the footprint creates a multi-vendor ecosystem for single-stage power conversion units for 48Vin to low voltage, high current applications.
Each of these architectures offers different benefits based on the requirements of your data processing environment. ST looks forward to working with you to deliver an optimized power architecture based on your specific data center design priorities.