The International Solid-State Circuits Conference (ISSCC) is the self-proclaimed “foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip. It is the flagship conference of the IEEE Solid-State Circuits Society and an annual “opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency” and an important venue for the presentation of top-shelf industry progress. This year, ISSCC takes place Feb 11-15 in San Francisco.
Naturally, ST will be there. Our engineers are on the ISSCC docket to present a range of key developments and achievements. In case you are attending — and even more, if you are not — here is a list of forums, workshops, and papers in which ST is presenting and/or has contributed.
Sunday, Feb 11th
— Forum 2 is a full-day session focused on FinFETs & FD-SOI – A Mixed-Signal Circuit Designer’s Perspective.
With circuit design in the nanometer regime, designers have to choose between implementing their solid-state circuits in FinFET or FD-SOI technology. This Forum has assembled experts to discuss the opportunities these technologies present for designers. Experts will present the physics/modeling of FinFETs & FD-SOI transistors and offer in-depth analyses of design considerations for modules spanning analog/mixed-signal to mm-Wave regimes. They’ll conclude the forum with a panel discussion. Having been a leading proponent of FD-SOI, ST’s Patrick Scheer will lead a session on FD-SOI Basics – Physics, Device Performance, and RF & mm-Wave Design Enablement at 10:15a
Later on Sunday, at 6p, Workshop2 is slated as a “Workshop for Circuits for Social Good” and aims to highlight the myriad ways that “circuits can help address some of the most important challenges facing society today.” The challenges range from health care to energy conservation and the workshop program was assembled “to give a broad perspective on how one can have a meaningful societal impact.” ST Fellow Andreia Cathelin, recently profiled in an, will lead a “Talk to an Expert” Roundtable on Careers in Industry at 7:30p.
In the Technical Sessions at ISSCC, ST will present and/or has contributed to:
On Monday, Feb 12
— Session 6: Ultra-High-Speed Wireline (Beginning at 1:30p)
—- Paper 6.6: A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR Transceiver in 28nm FD-SOI CMOS — Scheduled for 4:15p
On Tuesday, Feb 13
— Session 8: Wireless Power and Harvesting (Beginning at 8:30a)
—- Paper 8.8: A 30nA Quiescent 80nW-to-14mW Power-Range Shock-Optimized SECE-Based Piezoelectric Harvesting Interface with 420% Harvested-Energy Improvement — Scheduled for 11:15a
— Session 17: Technologies for Health and Society (Beginning at 1:30p)
—- Paper 17.8: A 665μW Silicon Photomultiplier-Based NIRS/EEG/EIT Monitoring ASIC for Wearable Functional Brain Imaging — Scheduled for 4:30p
On Wednesday, Feb 14
— Session 18: Adaptive Circuits and Digital Regulators (Beginning at 8:30a)
—- Paper 18.3: A 2.5μW 0.0067mm2 Automatic Back-Biasing Compensation Unit Achieving 50% Leakage Reduction in FD-SOI 28nm over 0.35-to-1V VDD Range — Scheduled for 9:30a
— Session 21: Extending Silicon and its Applications (Beginning at 10:15a)
—- Paper 21.4: A 10Gb/s Si-Photonic Transceiver with 150μW 120μs-Lock-Time Digitally Supervised Analog Micro-ring Wavelength Stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks — Scheduled for 11:15a
— Session 23: L0 Generation (Beginning at 10:15a)
—- Paper 23.4: A 301.7-to-331.8GHz Source with Entirely On-Chip Feedback Loop for Frequency Stabilization in 0.13μm BiCMOS — Scheduled for 11:15a
— Session 27: Power-Converter Techniques (Beginning at 1:30p)
—- Paper 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio — Scheduled for 2:30p
On Thursday, Feb 15
— Forum 5: Advanced Optical Communication: From Devices, Circuits, and Architectures to Algorithms (Full-day forum beginning at 8:00a
—- Insights Into Silicon Photonics Electro-Optical Transceiver Front-Ends — Scheduled for 9:20a