The STM32WL is the world’s first wireless microcontroller to integrate a LoRa transceiver on its silicon die. Until now, the industry either had discrete MCUs and transceivers, or both components under the same package but on different dies (System-in-Package). The new device opens the door to original applications by enabling simpler, more flexible, more integrated, and more power-efficient designs. The first STM32WLs we are launching today target OEMs and select ST customers who will also have access to a LoRAWAN stack on demand, thus accelerating their production ramp-ups. Let’s, therefore, understand better why the industry is so enthusiastic about a LoRa-enabled System-on-Chip and the ST optimizations that make the STM32WL special.
Why LoRa in an STM32 MCU?
In a survey presented at the 2017 International Symposium on Signals, Circuits, and Systems1￼, researchers established that LoRa could solve the significant challenges that plague the widespread adoption of IoT devices. Its use of sub-gigahertz frequencies along with its Chirp Spread Spectrum modulation technique enables the transmission of small packages over long distances while making it more resilient against interferences and more robust overall. In fact, in another paper published in the International Journal of Electrical Power & Energy Systems2, Chinese scholars show that LoRa is an excellent modulation for smart grids and provides a methodology to optimize the implementation of smart meters. They also make the point that smart grids are a great tool to reduce greenhouse gas emissions and meet the latest European standards. The STM32WL is thus an essential step toward the democratization of the Long Range (LoRa) technology.
Why is the STM32WL More Flexible? Dual Output Power and Multiple Modulation
The new device embeds a specially engineered radio based on Semtech SX126x that offers two power outputs: one up to 15 dBm and the other up to 22 dBm. Additionally, since the transceiver offers a linear frequency range from 150 MHz to 960 MHz, it is possible to use the STM32WL in every region of the world. For instance, European standards demand that LoRa systems use the lower output and a frequency of 868 MHz while North America can go up to 22 dBm and requires 915 MHz. Developers can thus tailor the STM32WL series to their particular region, optimize its performance, and easily open their system to other countries. Additionally, Being able to qualify one component for the STM32 MCU and the transceiver will save time and reduce the bill of materials as well as operating costs.
The sub-gigahertz transceiver of the STM32WL is compatible with LoRa, (G)FSK, (G)MSK, and BPSK modulation schemes. It’s easy to underestimate the scope of this feature. However, it means the STM32WL can run both a LoRaWAN stack, through LoRa modulation, and a Sigfox stack thanks to its support of Binary Phase Shift Keying (BPSK). Companies no longer have to choose between one or the other. Compatibility with (G)FSK and (G)MSK, and BPSK signifies that the STM32WL will also work with proprietary protocols that are popular among organizations looking to create unique solutions. Supporting all these modulations thus adds to the flexibility and international appeal of the STM32WL.
Why is the STM32WL So Efficient? Architecture Optimizations and Memory Headroom
The STM32WL benefits from optimizations introduced on the STM32WB, the STM32 MCU that integrates a Bluetooth module, and that became available in 2019. Traditionally, engineers need two 32 MHz external crystals: one that synchronizes with the Cortex-M4 and another for the LoRa transceiver. Thanks to our architectural implementations, the system only needs one crystal for the high-speed clock of the MCU and the radio, thus contributing to the reduction of the bill of materials and the PCB design simplification.
We optimized power management by including a switched-mode power supply and an LDO to shorten the STM32WL’s wake-up from any low-power mode. It usually takes about 60 µs to get such SMPS ready, but thanks to the presence of the LDO, the MCU can wake in 5 µs or less even if the SMPS isn’t ready yet. When taking the STM32WL out of sleep, stop, or standby, the system first uses the LDO and can start processing information while waiting for the SMPS to get ready.
ST planned for various memory needs and will have devices with 64 KB, 128 KB, and 256 KB of Flash to meet the applicative needs of various developers while also helping them meet their cost targets. Teams could thus write their software on a larger test model without worrying too much about running out of resources, then take the time to optimize their code to run on a smaller memory footprint. Having the LoRa radio on the same die as the STM32 MCU also makes the pin configuration simpler thanks to an upcoming version of STM32CubeMX.
How To Prepare for the STM32WL?
Enthusiasts or professionals looking to prepare for the mass market availability of the STM32WL can start working on an STM32L4 Nucleo board and a Semtech expansion board such as the SX1262DVK1DAS, the SX1262DVK1CAS or the SX1262DVK1BAS. The STM32L4 is close to the Cortex-M4 present in the STM32WL, and developers can experiment with its security and safety features, such as memory protection, private key acceleration, true random number generator, error correction system, and watchdogs, among many others. Porting the code to the STM32WL will require changes, but they will be minimal, thus enabling teams to get a leg up on the competition. The devices shipping to OEM today use a BGA housing but a wider variety of packages will be available by the end of 2020, along with a Sigfox stack.
- A. Lavric and V. Popa, “Internet of Things and LoRa™ Low-Power Wide-Area Networks: A survey,” 2017 International Symposium on Signals, Circuits and Systems (ISSCS), Iasi, 2017, pp. 1-5. doi: 10.1109/ISSCS.2017.8034915 ↩︎
- Lain-Chyr Hwang, Chao-Shun Chen, Te-Tien Ku, Wei-Cheng Shyu, “A bridge between the smart grid and the Internet of Things: Theoretical and practical roles of LoRa”, International Journal of Electrical Power & Energy Systems Volume 113, 2019, Pages 971-981, ISSN 0142-0615, doi: 10.1016/j.ijepes.2019.06.001. ↩︎